RTL Design & Integration Engineer (On-site. Bengaluru, India)
Ixana
RTL Design & Integration Engineer | SoC & ASIC Development
Build the next generation of ultra-low-power, brain-inspired compute systems powered by Wi-R.
📍 On-site – Bengaluru, India | Competitive salary + bonus + early equity
🚀 About Ixana
Ixana is a Purdue University spinoff pioneering brain-inspired wearable and edge computing. We’ve developed Wi-R, a patented communication technology that’s 100× more energy-efficient than Bluetooth or Wi-Fi. Join our 60-member team designing real-time, AI-powered human-computer interfaces for the next decade.
💡 The Wi-R Revolution
Wi-R is our patented non-radiative near-field communication technology that enables secure, “wire-like wireless” connectivity through tiny E-field bubbles around the human body.
This breakthrough delivers sub-0.1 nJ/bit communication—unlocking practical, long-duration wearable, implantable, and edge compute systems.
See Wi-R in action on our website.
🔧 What You’ll Do
Join our SoC development team to architect and integrate digital systems for next-gen compute platforms.
You will:
Perform RTL integration of internal/external IPs and subsystems into top-level SoCs.
Develop and maintain RTL wrappers, interconnect logic, and clock/reset infrastructures.
Run lint, CDC, and early synthesis checks to ensure high-quality integration.
Collaborate closely with design, verification, and physical design teams to ensure clean handoff.
Debug simulation and synthesis issues at both block and chip levels.
Maintain and automate integration flows using Python/Perl/Tcl.
Contribute to design reviews and document integration flows.
🎯 What We're Looking For
2–6 years of experience in RTL design and SoC/IP integration.
Strong RTL skills using Verilog/SystemVerilog.
Experience with AXI/AHB/APB protocols and interconnect architectures.
Hands-on experience with tools like Synopsys Design Compiler, Spyglass, or similar.
Proficiency in scripting languages (Python, Perl, Tcl) for flow automation.
Understanding of synthesis, timing, and SoC assembly flows.
Bonus Skills
Exposure to UPF/CPF and low-power design methodologies.
Experience with SoC integration frameworks and custom EDA automation.
Familiarity with high-performance, low-power compute architectures.
💰 Compensation & Benefits
Competitive base salary aligned with experience
Cash bonus + meaningful early-stage equity
Relocation support, partner job-search assistance
Medical, dental, vision coverage; generous PTO
Inventor awards for patents and contributions
🌟 Why Join Us
Work on cutting-edge deep tech that shapes the future of human-computer interaction
Collaborate with world-class SoC, RF, mixed-signal, and wearable computing engineers
Full ownership from architecture to silicon
Fast-paced, transparent, and deeply technical culture
Global exposure and opportunities to grow into lead roles
📍 Location
On-site — Bengaluru, India
📢 Application Requirements
Resume
Short note on a digital design or integration challenge you’ve solved
Ready to design the SoCs powering next-generation AI wearables?
Apply via our careers page.
In your note, tell us how you envision using Wi-R-enabled SoCs to redefine computing across consumer, industrial, and healthcare applications.
Keywords: RTL Design, SoC Integration, ASIC, Verilog, SystemVerilog, AXI, AHB, APB, Synthesis, Low-Power Design, UPF, EDA Automation, Python, Tcl, Digital Design, Startup, Equity, Wi-R, Human-Computer Interaction